A major advance in achieving higher levels of integration is the expansion of chip size through the use of redundancy. Lasers have been used for this purpose principally for polysilicon removal as in the case of 64K RAMs.1 Unfortunately such a deletive technique by Itself is inadequate to provide the interconnect flexibility needed to restructure general purpose logic by excising defective cells and wiring in redundant ones. In practice, an additive linking technology is essential to test successfully individual modular sections prior to rerouting interconnect wiring and to correct errors introduced in the routing process itself. Lincoln Laboratory is using the energy in a laser pulse to create a conducting path through an insulating layer separating a grid of isolated but overlapping bus lines.
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