Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

Methodology for Power-Aware Coherent Receiver Design

Not Accessible

Your library or personal account may give you access

Abstract

We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area.

© 2013 Optical Society of America

PDF Article
More Like This
ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers

Christoffer Fougstedt, Oscar Gustafsson, Cheolyong Bae, Erik Börjeson, and Per Larsson-Edefors
Th2A.38 Optical Fiber Communication Conference (OFC) 2020

Reducing the Power Consumption of the CMA Equalizer Update for a Digital Coherent Receiver

Daniel Cardenas, Domaniç Lavery, Philip Watts, and Seb J. Savory
Th4D.5 Optical Fiber Communication Conference (OFC) 2014

Reducing Equalizer Complexity in Coherent Receivers for Nyquist Spectrally Shaped Systems with Matched Filters

Junyi Wang, Chongjin Xie, and Z. Pan
OTu2I.3 Optical Fiber Communication Conference (OFC) 2013

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All rights reserved, including rights for text and data mining and training of artificial technologies or similar technologies.