A high-accuracy fiber-optic array processor (FOAP) based on the algorithm of digital multiplication by analog convolution is proposed. The FOAP architecture is a local regularly interconnected processor that utilizes an array of identical all-optical elemental-processing lattice units, namely, an optical splitter, an optical combiner, and a binary programmable fiber-optic transversal filter. Various FOAP matrix multipliers are proposed for nonnegative and twos-complement binary arithmetic matrix–vector, matrix–matrix, triple-matrix, and high-order matrix operations. The overall performances of the FOAP matrix multipliers are compared with the time-integrating and space-integrating architectures and with the digital multipliers. Extension of the digital-multiplication-by-analog-convolution algorithm is also considered.

Demetri Psaltis and Ravindra A. Athale Appl. Opt. 25(18) 3071-3077 (1986)

References

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b is the base used, n is the digits of accuracy, N is the number of optical convolvers of Fig. 5, N_{ADC} is the ADC resolution bits, MOPS is mega operations per second, and R_{1} is the Psaltis–Athale ratio.

Table 2

Performance Comparison of Several Optical Matrix–Vector Multipliers

1-D SI, one-dimensional space integrating; 1-D TI, one-dimensional time integrating; FM, frequency multiplexed; 1-D OP, outer products with one-dimensional modulators; 2-D OP, outer products with two-dimensional modulators; FOAP, fiber-optic array processor of Fig. 5.
Parameters for the product of an M × N matrix and an N × 1 vector to n digits of accuracy.
Assuming a 100-MHz clock rate; MOPS, mega operations per second for (n = 32, M = N = 128).

Table 3

Performance Comparison of Several Optical Matrix–Matrix Multipliers

SI, space integrating; TI, time integrating; 1-D OP, outer products with one-dimensional modulators; 2-D OP, outer products with two-dimensional modulators; FOAP, fiber-optic array processor of Fig. 6.
Parameters for the product of an M × N matrix and an N × P vector to n digits of accuracy.
Assuming a 100-MHz clock rate; GOPS, giga operations per second for (n = 32, M = N = P = 128).

Tables (3)

Table 1

Performance Comparison for Case Studies of the Fiber-Optic Array-Processor Matrix–Vector Multiplier of Fig. 5 for 32-bit (m = 32) Multiplications^{a}

b is the base used, n is the digits of accuracy, N is the number of optical convolvers of Fig. 5, N_{ADC} is the ADC resolution bits, MOPS is mega operations per second, and R_{1} is the Psaltis–Athale ratio.

Table 2

Performance Comparison of Several Optical Matrix–Vector Multipliers

1-D SI, one-dimensional space integrating; 1-D TI, one-dimensional time integrating; FM, frequency multiplexed; 1-D OP, outer products with one-dimensional modulators; 2-D OP, outer products with two-dimensional modulators; FOAP, fiber-optic array processor of Fig. 5.
Parameters for the product of an M × N matrix and an N × 1 vector to n digits of accuracy.
Assuming a 100-MHz clock rate; MOPS, mega operations per second for (n = 32, M = N = 128).

Table 3

Performance Comparison of Several Optical Matrix–Matrix Multipliers

SI, space integrating; TI, time integrating; 1-D OP, outer products with one-dimensional modulators; 2-D OP, outer products with two-dimensional modulators; FOAP, fiber-optic array processor of Fig. 6.
Parameters for the product of an M × N matrix and an N × P vector to n digits of accuracy.
Assuming a 100-MHz clock rate; GOPS, giga operations per second for (n = 32, M = N = P = 128).