Abstract

This paper presents a proposal of an optically reconfigurable gate array using a colored configuration. The optically reconfigurable gate array consists of a very-large-scale integration (VLSI), a holographic memory, and four lasers with different wavelengths. The optically reconfigurable gate array VLSI includes a fine-grained programmable gate array as well as field programmable gate arrays. Four configuration contexts can be stored on the holographic memory and can be programmed onto the programmable gate array VLSI addressed by the four lasers. This paper presents the demonstration of the optically reconfigurable gate array using a colored configuration.

© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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References

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  1. C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
    [Crossref]
  2. B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
    [Crossref]
  3. M. Ruba, R. Nemes, and C. Martis, “FPGA based real-time electric power assisted steering motor-drive simulator designed for HiL testing in the automotive industry,” in IEEE Vehicle Power and Propulsion Conference (2017), pp. 1–6.
  4. B. Poudel, N. K. Giri, and A. Munir, “Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS,” in IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (2017), pp. 28–36.
  5. B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.
  6. J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.
  7. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
    [Crossref]
  8. S. Kubota and M. Watanabe, “A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory,” IEEE Photonics J. 3, 665–675 (2011).
    [Crossref]
  9. H. Shinba and M. Watanabe, “Optically reconfigurable gate array platform for mono-instruction set computer architecture,” in IEEE Annual Computing and Communication Workshop and Conference (2017), pp. 1–4.

2016 (1)

C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
[Crossref]

2012 (1)

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

2011 (1)

S. Kubota and M. Watanabe, “A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory,” IEEE Photonics J. 3, 665–675 (2011).
[Crossref]

2009 (1)

Bahr, B.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

Banna, S.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

Chan, W. M.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Chang, J.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Chen, Y. H.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Cheng, H.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Chiang, M. C.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Denby, B.

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

Dieuleveult, F. D.

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

Fujiwara, H.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Giri, N. K.

B. Poudel, N. K. Giri, and A. Munir, “Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS,” in IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (2017), pp. 28–36.

He, Y.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

Hung, J.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Krivokapic, Z.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

Kubota, S.

S. Kubota and M. Watanabe, “A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory,” IEEE Photonics J. 3, 665–675 (2011).
[Crossref]

Kyrkou, C.

C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
[Crossref]

Lee, R.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Li, Q.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Liao, H. J.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Liaw, J. J.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Lin, C. Y.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Lin, J. Y.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Lin, K. C.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Martis, C.

M. Ruba, R. Nemes, and C. Martis, “FPGA based real-time electric power assisted steering motor-drive simulator designed for HiL testing in the automotive industry,” in IEEE Vehicle Power and Propulsion Conference (2017), pp. 1–6.

Munir, A.

B. Poudel, N. K. Giri, and A. Munir, “Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS,” in IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (2017), pp. 28–36.

Nakajima, M.

Nemes, R.

M. Ruba, R. Nemes, and C. Martis, “FPGA based real-time electric power assisted steering motor-drive simulator designed for HiL testing in the automotive industry,” in IEEE Vehicle Power and Propulsion Conference (2017), pp. 1–6.

Poudel, B.

B. Poudel, N. K. Giri, and A. Munir, “Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS,” in IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (2017), pp. 28–36.

Romain, O.

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

Ruba, M.

M. Ruba, R. Nemes, and C. Martis, “FPGA based real-time electric power assisted steering motor-drive simulator designed for HiL testing in the automotive industry,” in IEEE Vehicle Power and Propulsion Conference (2017), pp. 1–6.

Shinba, H.

H. Shinba and M. Watanabe, “Optically reconfigurable gate array platform for mono-instruction set computer architecture,” in IEEE Annual Computing and Communication Workshop and Conference (2017), pp. 1–4.

Singh, S. P.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

Theocharides, T.

C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
[Crossref]

Tietche, B. H.

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

Ttofis, C.

C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
[Crossref]

Watanabe, M.

S. Kubota and M. Watanabe, “A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory,” IEEE Photonics J. 3, 665–675 (2011).
[Crossref]

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
[Crossref]

H. Shinba and M. Watanabe, “Optically reconfigurable gate array platform for mono-instruction set computer architecture,” in IEEE Annual Computing and Communication Workshop and Conference (2017), pp. 1–4.

Weinstein, D.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

Wu, S. Y.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

IEEE Photonics J. (1)

S. Kubota and M. Watanabe, “A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory,” IEEE Photonics J. 3, 665–675 (2011).
[Crossref]

IEEE Trans. Comput. (1)

C. Ttofis, C. Kyrkou, and T. Theocharides, “A low-cost real-time embedded stereo vision system for accurate disparity estimation based on guided image filtering,” IEEE Trans. Comput. 65, 2678–2693 (2016).
[Crossref]

IEEE Trans. Consumer Electron. (1)

B. H. Tietche, O. Romain, B. Denby, and F. D. Dieuleveult, “FPGA-based simultaneous multichannel FM broadcast receiver for audio indexing applications in consumer electronics scenarios,” IEEE Trans. Consumer Electron. 58, 1153–1161 (2012).
[Crossref]

J. Lightwave Technol. (1)

Other (5)

H. Shinba and M. Watanabe, “Optically reconfigurable gate array platform for mono-instruction set computer architecture,” in IEEE Annual Computing and Communication Workshop and Conference (2017), pp. 1–4.

M. Ruba, R. Nemes, and C. Martis, “FPGA based real-time electric power assisted steering motor-drive simulator designed for HiL testing in the automotive industry,” in IEEE Vehicle Power and Propulsion Conference (2017), pp. 1–6.

B. Poudel, N. K. Giri, and A. Munir, “Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS,” in IEEE 28th International Conference on Application-Specific Systems, Architectures and Processors (2017), pp. 28–36.

B. Bahr, Y. He, Z. Krivokapic, S. Banna, and D. Weinstein, “32GHz resonant-fin transistors in 14  nm FinFET technology,” in IEEE International Solid—State Circuits Conference (2018), pp. 348–350.

J. Chang, Y. H. Chen, W. M. Chan, S. P. Singh, H. Cheng, H. Fujiwara, J. Y. Lin, K. C. Lin, J. Hung, R. Lee, H. J. Liao, J. J. Liaw, Q. Li, C. Y. Lin, M. C. Chiang, and S. Y. Wu, “A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications,” in IEEE International Solid-State Circuits Conference (2017), pp. 206–207.

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Figures (9)

Fig. 1.
Fig. 1. Block diagram of an optically reconfigurable gate array using a colored configuration.
Fig. 2.
Fig. 2. Photograph of a 0.18 μm CMOS process optically reconfigurable gate array VLSI.
Fig. 3.
Fig. 3. Block diagram of experimental systems. (a) Blue laser ( λ = 404  nm ), (b) green laser ( λ = 532  nm ), (c) red laser ( λ = 632.8  nm ), and (d) red laser ( λ = 642  nm ).
Fig. 4.
Fig. 4. Photograph of the experimental systems. (a) Blue laser ( λ = 404  nm ), (b) green laser ( λ = 532  nm ), (c) red laser ( λ = 632.8  nm ), and (d) red laser ( λ = 642  nm ).
Fig. 5.
Fig. 5. Color holographic memory pattern recording four configuration contexts of an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit respectively responding to a 404 nm laser, a 532 nm laser, a 632.8 nm laser, and a 642 nm laser.
Fig. 6.
Fig. 6. Block diagram of the experimental system.
Fig. 7.
Fig. 7. Photograph of the experimental system.
Fig. 8.
Fig. 8. CCD-captured configuration context patterns of an AND circuit, an OR circuit, an EXOR circuit, and a NOR circuit addressed by (a) 404 nm, (b) 532 nm, (c) 632.8 nm, and (d) 642 nm lasers, respectively.
Fig. 9.
Fig. 9. Waveforms of (a) AND circuit, (b) OR circuit, (c) EXOR circuit, and (d) NOR circuit operations on the optically reconfigurable gate array VLSI.

Tables (2)

Tables Icon

Table 1. Specifications of the ORGA-VLSI

Tables Icon

Table 2. Configuration Speed of a Full System Including Beam Splitters

Equations (2)

Equations on this page are rendered with MathJax. Learn more.

H color ( α , β ) = j = 1 L N i = 1 B N ( j ) cos ( π λ j L { ( α x j i ) 2 + ( β y j i ) 2 } ) .
H color ( α , β ) = H color ( α , β ) H min H max H min .

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