Abstract

In this paper, we design and fabricate a 32-GS/s 6-bit digital-to-analog convertor (DAC) based on SiGe technology. The DAC uses double sampling technique and segment current steering architecture to achieve high dynamic linearity. A corrector circuit is proposed to suppress the duty cycle error for linearity optimization. The spurious free dynamic range (SFDR) is above 31.5 dBc over the Nyquist bandwidth at the sampling rate of 32-GS/s. A full-rate input interface is integrated to realize data exchange with field-programmable gate array (FPGA). The experimental results show that the net data rate of 50-Gb/s orthogonal frequency division multiplexing (OFDM) signals with non-uniform quantization can be generated by the designed and fabricated DAC. The OFDM signal transmission over 10-km standard single mode fiber (SSMF) with 64-quadrature amplitude modulation (QAM) and 128-QAM formats have been successfully achieved.

© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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References

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  1. D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.
    [Crossref]
  2. S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.
  3. M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.
  4. M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
    [Crossref]
  5. T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.
  6. M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
    [Crossref]
  7. A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
    [Crossref]
  8. A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).
  9. Socionext, http://socionextus.com/products/networking-asic/adc-dac/ .
  10. L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.
  11. M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).
  12. T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).
  13. E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
    [Crossref]
  14. Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).
    [Crossref] [PubMed]
  15. J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
    [Crossref]
  16. C. Brokish and M. Lewis, Texas Instruments Digital Processing Solutions (Texas, 1997), Chap. 2.
  17. P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).
    [Crossref]
  18. F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.
    [Crossref]

2017 (1)

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

2016 (2)

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).
[Crossref] [PubMed]

2015 (1)

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
[Crossref]

2011 (2)

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

2006 (1)

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

2004 (1)

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

1996 (1)

P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).
[Crossref]

Aguirre, J.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Alarcon, E.

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

Albiol, M.

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

Alpert, T.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

Annema, A.

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
[Crossref]

Balteanu, A.

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

Baranauskas, D.

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.
[Crossref]

Berroth, M.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

Besson, M.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Cao, J.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Catli, B.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Chen, T.

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

Choe, M.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Cui, D.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Duncan, L.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Dupaix, B.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Ellinger, F.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

Falt, C.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Ferenci, D.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

Flemeke, P.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Gibbins, R.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Gielen, G. E.

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

Gonzalez, J. L.

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

Grozing, M.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

Gustat, H.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

Halder, S.

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

Han, L.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

He, T.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Hu, K.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Huang, Z.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Khafaji, M.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

Khalil, W.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Lang, F.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

LaRue, M.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Li-Wei, Z.

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.
[Crossref]

Mathieu, B.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

McCue, J.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Momtaz, A.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Murata, K.

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Nagatani, M.

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Naim, B.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Nauta, B.

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
[Crossref]

Nazemi, A.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Nosaka, H.

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Olieman, E.

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
[Crossref]

Peng, J.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

Pollex, D.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Qiu, C.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

Sadot, D.

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).
[Crossref] [PubMed]

Sano, K.

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Scheunders, P.

P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).
[Crossref]

Scheytt, C.

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

Scheytt, J.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

Schvan, P.

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Sedighi, B.

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

Sheng, F.

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.
[Crossref]

Singh, U.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Sorin, P.

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

Su, Y.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

Szilagyi, S.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Teshome, M.

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

Tremblay, C.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

Wang, S.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Xu-Jian, L.

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.
[Crossref]

Yamanaka, S.

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Yariy, M.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

Yoffe, Y.

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).
[Crossref] [PubMed]

Zelenin, D.

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.
[Crossref]

Zhang, B.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Zhang, Y.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

Zhu, Q.

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

IEEE J. Solid-State Circuits (1)

E. Olieman, A. Annema, and B. Nauta, “An interleaved full nyquist high-speed DAC technique,” IEEE J. Solid-State Circuits 50(3), 704–713 (2015).
[Crossref]

IEEE Photonics J. (1)

J. Peng, L. Han, Q. Zhu, C. Qiu, Y. Zhang, C. Tremblay, and Y. Su, “SQNR improvement enabled by nonuniform DAC output levels for IM-DD OFDM systems,” IEEE Photonics J. 9(2), 1–11 (2017).
[Crossref]

IEEE Trans. Circuits And Systems—I. Regular Papers (1)

M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Trans. Circuits And Systems—I. Regular Papers 51(1), 159–169 (2004).

IEEE Trans. Circuits Syst. (1)

T. Chen and G. E. Gielen, “The analysis and improvement of a current-steering DACs dynamic SFDR—I: the cell-dependent delay differences,” IEEE Trans. Circuits Syst. 53(1), 3–15 (2006).

IEEE Trans. Microw. Theory Tech. (1)

M. Khafaji, H. Gustat, B. Sedighi, F. Ellinger, and J. Scheytt, “A 6-bit fully binary digital-to-analog converter in 0.25-m SiGe BiCMOS for optical communications,” IEEE Trans. Microw. Theory Tech. 59(9), 2254–2264 (2011).
[Crossref]

IEEE Trans. Microwave Theory Tech. (1)

A. Balteanu, P. Schvan, and P. Sorin, “A 6-bit segmented DAC architecture with up to 56-GHz sampling clock and 6-V differential swing,” IEEE Trans. Microwave Theory Tech. 64(3), 881–891 (2016).

J. Solid-State Circuits (1)

M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, and K. Murata, “Ultrahigh-speed low power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems,” J. Solid-State Circuits 46(10), 2215–2225 (2011).
[Crossref]

Opt. Express (1)

Y. Yoffe and D. Sadot, “Novel low resolution ADC-DSP optimization based on non-uniform quantization and MLSE for data centers interconnects,” Opt. Express 24(5), 5346–5354 (2016).
[Crossref] [PubMed]

Pattern Recognit. Lett. (1)

P. Scheunders, “A genetic Lloyd-max image quantization algorithm,” Pattern Recognit. Lett. 17(5), 547–556 (1996).
[Crossref]

Other (9)

F. Sheng, L. Xu-Jian, and Z. Li-Wei, “A Lloyd-max-based non-uniform quantization scheme for distributed video coding,” in 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (IEEE, 2007), pp. 848–853.
[Crossref]

C. Brokish and M. Lewis, Texas Instruments Digital Processing Solutions (Texas, 1997), Chap. 2.

A. Nazemi, K. Hu, B. Catli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao, “A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS,” in International Solid-State Circuits Conference (IEEE, 2015), pp. 1–3.
[Crossref]

Socionext, http://socionextus.com/products/networking-asic/adc-dac/ .

L. Duncan, B. Dupaix, J. McCue, B. Mathieu, M. LaRue, M. Teshome, M. Choe, and W. Khalil, “A 10b DC-to-20 GHz multiple-return-to-zero DAC with >48dB SFDR,” in International Solid-State Circuits Conference (IEEE, 2017), pp. 286–287.

T. Alpert, F. Lang, D. Ferenci, M. Grozing, and M. Berroth, “A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS,” in MTT-s International Microwave Symposium (IEEE, 2011), pp. 1–4.

D. Baranauskas and D. Zelenin, “A 0.36W 6b up to 20GS/s DAC for UWB wave formation,” in International Solid-State Circuits Conference (IEEE, 2006), pp. 2380– 2389.
[Crossref]

S. Halder, H. Gustat, and C. Scheytt, “A 20GS/s 8-bit current steering DAC in 0.25µm SiGe BiCMOS technology,” in Proc. European Microwave Integrated Circuits Conference (2008), pp. 147–150.

M. Yariy, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, B. Naim, R. Gibbins, and P. Schvan, “A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory,” in International Solid-State Circuits Conference (IEEE, 2011), pp. 194–196.

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Figures (10)

Fig. 1
Fig. 1 Top block diagram of DAC.
Fig. 2
Fig. 2 Architecture of six-lane data interface.
Fig. 3
Fig. 3 (a) Architecture of DAC core, (b) One lane of 2-1 MUXs.
Fig. 4
Fig. 4 Block diagram of clock distributed circuit.
Fig. 5
Fig. 5 Chip die Micrograph of the DAC.
Fig. 6
Fig. 6 Experiment setup for chip test.
Fig. 7
Fig. 7 (a) Measured DNL versus output code, (b) Measured INL versus output code.
Fig. 8
Fig. 8 Measured SFDR vs output frequency at 32-GS/s.
Fig. 9
Fig. 9 Experimental setup of the IM-DD optical OFDM fiber transmission link. Inset (a)-(c): analog signal and the quantized signal based on uniform, A-law and Lloyd quantization schematics. Inset (I)-(III): EVM based on uniform, A-law and Lloyd quantization schematics.
Fig. 10
Fig. 10 Experiment results of the IM-DD optical OFDM fiber transmission link with three quantization schemes for (a) 5-bit 64-QAM, (b) 6-bit 64-QAM and (c) 6-bit 128-QAM formats and corresponding constellation formats.

Tables (1)

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Table 1 Performance Comparison of 6-bit DAC

Equations (2)

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F(y)=sign(y) | y |(1+ln(A)) A if | y |< 1 1+ln(A)
F(y)=sign(y) exp(| y |(1+ln(A))1) A if 1 1+ln(A) | y |<1

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