Abstract

We present a compact interferometer circuit to extract multiple model parameters of on-chip waveguides and directional couplers from optical measurements. The compact design greatly improves the accuracy of extraction with fewer measurements, making it useful for process monitoring and detailed wafer-level variability analysis. We discuss the design requirements and illustrate the extraction using the Restart-CMA-ES global optimization algorithm.

© 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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References

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  1. W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18(23), 23598 (2010).
    [Crossref]
  2. Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.
  3. W. Bogaerts, U. Khan, and Y. Xing, “Layout-aware yield prediction of photonic circuits,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.
  4. T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
    [Crossref]
  5. W. Bogaerts and L. Chrostowski, “Silicon Photonics Circuit Design: Methods, Tools and Challenges,” Laser Photonics Rev. 12(4), 1700237 (2018).
    [Crossref]
  6. S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
    [Crossref]
  7. S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental Extraction of Effective Refractive Index and Thermo-Optic Coefficients of Silicon-on-Insulator Waveguides Using Interferometers,” J. Lightwave Technol. 33(21), 4471–4477 (2015).
    [Crossref]
  8. Z. Lu, J. Jhoja, J. Klein, X. Wang, A. Liu, J. Flueckiger, J. Pond, and L. Chrostowski, “Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability,” Opt. Express 25(9), 9712 (2017).
    [Crossref]
  9. L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.
  10. X. Chen, Z. Li, M. Mohamed, L. Shang, and A. R. Mickelson, “Parameter extraction from fabricated silicon photonic devices,” Appl. Opt. 53(7), 1396 (2014).
    [Crossref]
  11. T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).
  12. Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
    [Crossref]
  13. Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.
  14. Y. Li, D. Vermeulen, Y. De Koninck, G. Yurtsever, G. Roelkens, and R. Baets, “Compact grating couplers on silicon-on-insulator with reduced backreflection,” Opt. Lett. 37(21), 4356–4358 (2012).
    [Crossref]
  15. Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).
  16. M. Fiers, T. Van Vaerenbergh, K. Caluwaerts, D. Vande Ginste, B. Schrauwen, J. Dambre, and P. Bienstman, “Time-domain and frequency-domain modeling of nonlinear optical components at the circuit-level using a node-based approach,” J. Opt. Soc. Am. B 29(5), 896 (2012).
    [Crossref]
  17. N. Hansen, “The cma evolution strategy: A tutorial,” arXiv preprint arXiv:1604.00772 (2016).
  18. “The CMA Evolution Strategy,” http://cma.gforge.inria.fr/ . Accessed: 2019-02-14.
  19. A. Auger and N. Hansen, “A restart cma evolution strategy with increasing population size,” in Evolutionary Computation, 2005. The 2005 IEEE Congress on, vol. 2 (IEEE, 2005), pp. 1769–1776.

2018 (2)

W. Bogaerts and L. Chrostowski, “Silicon Photonics Circuit Design: Methods, Tools and Challenges,” Laser Photonics Rev. 12(4), 1700237 (2018).
[Crossref]

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

2017 (2)

Z. Lu, J. Jhoja, J. Klein, X. Wang, A. Liu, J. Flueckiger, J. Pond, and L. Chrostowski, “Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability,” Opt. Express 25(9), 9712 (2017).
[Crossref]

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

2015 (1)

2014 (1)

2012 (2)

2010 (2)

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18(23), 23598 (2010).
[Crossref]

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Alves Júnior, A. R.

Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.

Auger, A.

A. Auger and N. Hansen, “A restart cma evolution strategy with increasing population size,” in Evolutionary Computation, 2005. The 2005 IEEE Congress on, vol. 2 (IEEE, 2005), pp. 1769–1776.

Baets, R.

Y. Li, D. Vermeulen, Y. De Koninck, G. Yurtsever, G. Roelkens, and R. Baets, “Compact grating couplers on silicon-on-insulator with reduced backreflection,” Opt. Lett. 37(21), 4356–4358 (2012).
[Crossref]

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Bienstman, P.

Bogaerts, W.

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

W. Bogaerts and L. Chrostowski, “Silicon Photonics Circuit Design: Methods, Tools and Challenges,” Laser Photonics Rev. 12(4), 1700237 (2018).
[Crossref]

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental Extraction of Effective Refractive Index and Thermo-Optic Coefficients of Silicon-on-Insulator Waveguides Using Interferometers,” J. Lightwave Technol. 33(21), 4471–4477 (2015).
[Crossref]

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

W. Bogaerts, U. Khan, and Y. Xing, “Layout-aware yield prediction of photonic circuits,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).

Caluwaerts, K.

Chen, X.

Chrostowski, L.

W. Bogaerts and L. Chrostowski, “Silicon Photonics Circuit Design: Methods, Tools and Challenges,” Laser Photonics Rev. 12(4), 1700237 (2018).
[Crossref]

Z. Lu, J. Jhoja, J. Klein, X. Wang, A. Liu, J. Flueckiger, J. Pond, and L. Chrostowski, “Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability,” Opt. Express 25(9), 9712 (2017).
[Crossref]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Dambre, J.

Daniel, L.

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

De Koninck, Y.

Dong, J.

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).

Dumon, P.

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental Extraction of Effective Refractive Index and Thermo-Optic Coefficients of Silicon-on-Insulator Waveguides Using Interferometers,” J. Lightwave Technol. 33(21), 4471–4477 (2015).
[Crossref]

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Dwivedi, S.

Fard, S. T.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Fiers, M.

Flueckiger, J.

Z. Lu, J. Jhoja, J. Klein, X. Wang, A. Liu, J. Flueckiger, J. Pond, and L. Chrostowski, “Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability,” Opt. Express 25(9), 9712 (2017).
[Crossref]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Hansen, N.

N. Hansen, “The cma evolution strategy: A tutorial,” arXiv preprint arXiv:1604.00772 (2016).

A. Auger and N. Hansen, “A restart cma evolution strategy with increasing population size,” in Evolutionary Computation, 2005. The 2005 IEEE Congress on, vol. 2 (IEEE, 2005), pp. 1769–1776.

Horikawa, T.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Jeong, S. H.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Jhoja, J.

Khan, U.

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

W. Bogaerts, U. Khan, and Y. Xing, “Layout-aware yield prediction of photonic circuits,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).

Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.

Kinoshita, K.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Klein, J.

Li, Y.

Li, Z.

Liu, A.

Lu, Z.

Melati, D.

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

Melloni, A. I.

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

Mickelson, A. R.

Mogami, T.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Mohamed, M.

Pond, J.

Roelkens, G.

Ruocco, A.

Schrauwen, B.

Selvaraja, S.

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Shang, L.

Shiina, A.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Shimura, D.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Sobu, Y.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Spuesens, T.

Takahashi, H.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Tokushima, M.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Trotter, D. C.

Ushida, J.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

Van Thourhout, D.

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

Van Vaerenbergh, T.

Vande Ginste, D.

Vanslembrouck, M.

Vermeulen, D.

Wang, X.

Z. Lu, J. Jhoja, J. Klein, X. Wang, A. Liu, J. Flueckiger, J. Pond, and L. Chrostowski, “Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability,” Opt. Express 25(9), 9712 (2017).
[Crossref]

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Wang, Y.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Watts, M. R.

Weng, T. W.

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

Wu, Y.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Xing, Y.

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

W. Bogaerts, U. Khan, and Y. Xing, “Layout-aware yield prediction of photonic circuits,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).

Yurtsever, G.

Zortman, W. A.

Appl. Opt. (1)

IEEE J. Sel. Top. Quantum Electron. (1)

S. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology,” IEEE J. Sel. Top. Quantum Electron. 16(1), 316–324 (2010).
[Crossref]

J. Lightwave Technol. (1)

J. Opt. Soc. Am. B (1)

Laser Photonics Rev. (1)

W. Bogaerts and L. Chrostowski, “Silicon Photonics Circuit Design: Methods, Tools and Challenges,” Laser Photonics Rev. 12(4), 1700237 (2018).
[Crossref]

Nanophotonics (1)

T. W. Weng, D. Melati, A. I. Melloni, and L. Daniel, “Stochastic simulation and robust design optimization of integrated photonic filters,” Nanophotonics 6(1), 299–308 (2017).
[Crossref]

Opt. Express (2)

Opt. Lett. (1)

Photonics Res. (1)

Y. Xing, J. Dong, S. Dwivedi, U. Khan, and W. Bogaerts, “Accurate extraction of fabricated geometry using optical measurement,” Photonics Res. 6(11), 1008 (2018).
[Crossref]

Other (9)

Y. Xing, U. Khan, A. R. Alves Júnior, and W. Bogaerts, “Behavior model for directional coupler,” in Proceedings Symposium IEEE Photonics Society Benelux, (2017), pp. 128–131.

L. Chrostowski, X. Wang, J. Flueckiger, Y. Wu, Y. Wang, and S. T. Fard, “Impact of fabrication non-uniformity on chip-scale silicon photonic integrated circuits,” in Conference on Optical Fiber Communication, Technical Digest Series, (OSA, 2014), pp. Th2A–37.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical Model for Spatial Variations of Integrated Photonics,” in IEEE International Conference on Group IV Photonics, (OSA, Cancun, Mexico, 2018).

N. Hansen, “The cma evolution strategy: A tutorial,” arXiv preprint arXiv:1604.00772 (2016).

“The CMA Evolution Strategy,” http://cma.gforge.inria.fr/ . Accessed: 2019-02-14.

A. Auger and N. Hansen, “A restart cma evolution strategy with increasing population size,” in Evolutionary Computation, 2005. The 2005 IEEE Congress on, vol. 2 (IEEE, 2005), pp. 1769–1776.

Y. Xing, J. Dong, U. Khan, and W. Bogaerts, “Hierarchical model for spatial variations of integrated photonics,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

W. Bogaerts, U. Khan, and Y. Xing, “Layout-aware yield prediction of photonic circuits,” in 2018 IEEE 15th International Conference on Group IV Photonics (GFP), (IEEE, 2018), pp. 1–2.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S. H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (IEEE, 2017).

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Figures (5)

Fig. 1.
Fig. 1. (a) The layout of the folded two-stage MZI. The circuit has two MZI stages connected by three DCs with an identical cross section for the straight coupling section and identical bends. We used low-reflection GCs [14] to reduce measurement noise due to parasitic back-reflections. The circuit has a compact footprint of 400 $\mathrm {\mu m}~\times ~$100 $\mathrm {\mu m}$. The large dotted frame indicates the region to extract process variation of the waveguide, and it covers an area of 120 $\mathrm {\mu m}~\times ~$40 $\mathrm {\mu m}$. The small dotted frame on the right indicates the region to extract process variation in the DC, and it covers three DCs with an area of 45 $\mathrm {\mu m}~\times ~$40 $\mathrm {\mu m}$. (b) The layout of the two MZIs to extract waveguide parameters used in [12]. The design has a footprint of 350 $\mathrm {\mu m}~\times ~$180 $\mathrm {\mu m}$. The region to extract process variations in the waveguide covers an area of 55 $\mathrm {\mu m}~\times ~$180 $\mathrm {\mu m}$. (c) The layout of the three MZIs to extract DC parameter used in [13]. The design has a footprint of 285 $\mathrm {\mu m}~\times ~$280 $\mathrm {\mu m}$. The region to extract process variation in the DC covers an area of 150 $\mathrm {\mu m}~\times ~$220 $\mathrm {\mu m}$.
Fig. 2.
Fig. 2. The circuit model of the device. Two MZI stages have different $n_{eff}$ and $n_{g}$ led by the local fabrication variation.
Fig. 3.
Fig. 3. A good match between simulated and measured spectra is achieved by the restart-CMA-ES method. Red: measured spectrum. Blue: simulated spectrum by CAPHE.
Fig. 4.
Fig. 4. (a) Locations of the folded two-stage MZIs on a die. (b) Extracted neff,2 and ng,2 of die (X=0, Y=0) (in the center of the wafer). (c) Extracted width map and (d) thickness map of the die. x and y indicate the locations of the MZIs on the die. Blue dots: extracted value. Green grid: fitted map of extracted values using a linear function.
Fig. 5.
Fig. 5. (a) Interpolated wafer map of (a) linewidth and (b) thickness extracted using the two-stage MZI circuits. 5841 black dots indicate the site of valid samples. Black rectangular grid indicates the boundary of dies. Black circle is the edge of the wafer.

Tables (3)

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Table 1. Obtained parameter values from spectral measurement and fitting uncertainties using the Restart CMA-ES method.

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Table 2. Extracted waveguide width and thickness of the high-order stage arm.

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Table 3. Statistics of measured width and thickness.

Equations (9)

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v a r i a t i o n t o t a l = v a r i a t i o n i n t e r d i e + v a r i a t i o n l o c a t i o n d e p e n d e n t + v a r i a t i o n l o c a l
Δ n e f f , t o t a l = n e f f w Δ w t o t a l + n e f f t Δ t t o t a l
Δ n e f f , l o c a l = ( n e f f w n g t n g w + n e f f t ) Δ t l o c a l
Δ n e f f , t o t a l = n e f f w Δ w t o t a l + n e f f t Δ t t o t a l = 0.0019   n m 1 × 30   n m + 0.0040   n m 1 × 10   n m = 0.097.
Δ n e f f , l o c a l = 0.0064   n m 1 × 0.8   n m × 2 = 0.0102 ,
n e f f ( λ ) = n e f f ( λ λ 0 ) n g n e f f λ 0
K c o u p l e d ( λ ) = s i n 2 ( κ ( λ ) L c o u p l e r + κ 0 ( λ ) )
κ ( λ ) = κ ( λ 0 ) + ( λ λ 0 ) κ λ ( λ 0 ) + 1 2 ( λ λ 0 ) 2 2 κ λ 2 ( λ 0 )
κ 0 ( λ ) = κ 0 + ( λ λ 0 ) κ 0 λ ( λ 0 ) + 1 2 ( λ λ 0 ) 2 2 κ 0 λ 2 ( λ 0 )

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